//registers 
module regs_mod(
	rst,
	clk,
	reg_read_addr,
	reg_read_addr1,
	reg_read_data,
	reg_read_data1,
	reg_write_addr,
	reg_write_data,
	reg_en_write
);
input rst;
input clk;
input reg_en_write;

input [4:0] reg_read_addr;
input [4:0] reg_read_addr1;
input [4:0] reg_write_addr;

output [31:0] reg_read_data;
output [31:0] reg_read_data1;
input [31:0] reg_write_data;

reg [31:0] reg_x [31:1];

reg [31:0] reg_read_data;
reg [31:0] reg_read_data1;
always @ ( * ) begin
	if ( reg_read_addr != 5'b0 )
		 reg_read_data <= reg_x[reg_read_addr];
	else if ( reg_read_addr == 5'b0)
		reg_read_data <= 32'b0;
	else;
	if ( reg_read_addr1 != 5'b0 )
		 reg_read_data1 <= reg_x[reg_read_addr1];
	else if ( reg_read_addr1 == 5'b0)
		reg_read_data1 <= 32'b0;
	else;
end

always @ ( posedge clk )
	if ( rst ) begin
		reg_x[1][31:0] <= 32'h0;
		reg_x[2][31:0] <= 32'h0;
		reg_x[3][31:0] <= 32'h0;
		reg_x[4][31:0] <= 32'h0;
		reg_x[5][31:0] <= 32'h0;
		reg_x[6][31:0]	<= 32'h0;	
		reg_x[7][31:0] <= 32'h0;
		reg_x[8][31:0] <= 32'h0;
		reg_x[9][31:0] <= 32'h0;
		reg_x[10][31:0] <= 32'h0;
		reg_x[11][31:0] <= 32'h0;
		reg_x[12][31:0] <= 32'h0;
		reg_x[13][31:0] <= 32'h0;
		reg_x[14][31:0] <= 32'h0;
		reg_x[15][31:0] <= 32'h0;
		reg_x[16][31:0] <= 32'h0;
		reg_x[17][31:0] <= 32'h0;
		reg_x[18][31:0] <= 32'h0;
		reg_x[19][31:0] <= 32'h0;
		reg_x[20][31:0] <= 32'h0;
		reg_x[21][31:0] <= 32'h0;
		reg_x[22][31:0] <= 32'h0;
		reg_x[23][31:0] <= 32'h0;
		reg_x[24][31:0] <= 32'h0;
		reg_x[25][31:0] <= 32'h0;
		reg_x[26][31:0] <= 32'h0;
		reg_x[27][31:0] <= 32'h0;
		reg_x[28][31:0] <= 32'h0;
		reg_x[29][31:0] <= 32'h0;
		reg_x[30][31:0] <= 32'h0;
		reg_x[31][31:0] <= 32'h0;
	end 
	else if ( reg_en_write == 1 && reg_write_addr != 5'b0 )
		  reg_x[reg_write_addr] <= reg_write_data;
	else;


endmodule
